1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device that uses a plurality of source voltages.
This application is based upon and claims the benefit of priority from Japanese patent applications No. 2007-138627 filed on May 25, 2007 and No. 2008-95835 filed on Apr. 2, 2008, the disclosure of which are incorporated herein in their entirety by reference.
2. Description of Related Art
It is well known that there is a semiconductor device which operates by using a plurality of types of internal source voltages. The semiconductor device selectively uses the plurality of internal source voltages depending on types of internal circuits. FIG. 1 is a block diagram showing an example of a structure of such typical semiconductor device. This semiconductor device 101 receives a source voltage VDD (e.g. 1.5 V) and a ground voltage GND (e.g. 0 V) supplied from outside. The semiconductor device 101 includes a memory macro 102, a step-down circuit 111, a step-down circuit 112, a reference power supply 113, a negative pump (N-pump) 114, and a positive pump (P-pump) 115.
The memory macro 102 is a DRAM core, which includes a cell array core 103 for storing data and a peripheral circuit 104 for controlling the cell array core 103. The cell array core 103 includes a plurality of cells arranged in matrix, a plurality of sense amplifiers, a word-line driving circuit, a bit-line precharge circuit, and a sense amplifier driving circuit. The peripheral circuit 104 includes a decoder and a controller.
The step-down circuit 111 reduces the source voltage VDD to generate a High-side source voltage VPD (e.g. 1.2 V) of a bit-line precharge transistor, and outputs it to the cell array core 103. The step-down circuit 112 decreases the source voltage VDD to generate a source voltage VSA (e.g. 1.0 V) for a sense amplifier SA, and outputs it to the cell array core 103. The reference power supply 113 reduces the source voltage VSA for the sense amplifier SA to generate a reference voltage HVDD (e.g. 0.5 V), and outputs it to the cell array core 103. The N-pump 114 reduces and inverts the source voltage VDD to generate a Low-side voltage VKK (e.g. −0.4 V) at the time of driving a word line and to generate a substrate potential VBB (e.g. −0.4 V) of a selection transistor, and outputs those to the cell array core 103. The P-pump 115 boosts up the source voltage VDD to generate a High-side voltage VPP (e.g. 2.5 V) at the time of driving the word line, and outputs it to the cell array core 103.
Conventionally, the source voltage VDD supplied to the entire circuits of the semiconductor device 101 is the same or higher voltage than the source voltage VSA that is supplied for the sense amplifier SA. Therefore, the source voltage VSA is generated directly from the source voltage VDD or generated by reducing the source voltage VDD. In a general-purpose DRAM, in particular, there is less number of bit-line divisions and the load capacity is large. Thus, an operating current Isa of the sense amplifier SA is large. Therefore, when comparing it with a word line current Iword, there is found a relation “Iword<Isa”. Thus, it is essential to generate the operating current Isa from the VDD power supply that has a sufficient current supply capability. There is also the same tendency found when generating other voltages. Lately, there are also cases where the source voltage VPP is supplied from outside, because the electric current efficiency is poor when the source voltage VPP for driving the word lines is generated from the source voltage VDD.
As an example of the semiconductor device that operates by using a plurality of types of source voltages, Japanese Laid-Open Patent Publication JP-A-Heisei 11-213667 discloses a semiconductor memory device. This semiconductor memory device includes an input circuit, a peripheral circuit, a memory array portion, a first internal step-down circuit, and a second internal step-down circuit. The memory array portion includes memory cells arranged in matrix. The first internal step-down circuit reduces source voltages supplied from an output circuit and an external terminal to generate a first internal voltage. The second internal step-down circuit reduces the source voltage supplied from the external terminal, and generates a second internal voltage that has an absolutely larger voltage value than the first internal voltage. When the semiconductor memory device operates as a first power supply version where the source voltage supplied from the external terminal is set to have an absolutely larger voltage value than the second internal voltage, the first internal voltage generated by the first internal step-down circuit is supplied to the memory array portion, the second internal voltage generated by the second step-down circuit is supplied to the input circuit and the peripheral circuit, and the source voltage is supplied to the output circuit. In the meantime, when the semiconductor memory device operates as a second power supply version where the source voltage supplied from the external terminal is set to have an equal voltage value as that of the second internal voltage, the first internal voltage generated by the first internal step-down circuit is supplied to the memory array portion, the output of the second internal step-down circuit is isolated from the input circuit and the peripheral circuit, and the source voltage is supplied to the input circuit, the peripheral circuit, and the output circuit.
We have now discovered the following facts. Recently, thickness of gate oxide films of transistors in logic circuits has been made thinner in order to achieve a high-speed operation/a low electric current. In that case, the source voltage VDD of the logic circuit in the case of FIG. 1 is reduced to 1.0 V or less. In the meantime, it is necessary for the source voltage VSA for the sense amplifier SA to be set as about 1.0 V, because of an operation limit voltage of the sense amplifier. In general, a voltage fluctuation of ±10% is tolerated for the source voltage VDD. When the source voltage VSA is to be generated from the source voltage VDD that has an apparent decrease in its voltage value, it becomes necessary to boost up the voltage for generating the source voltage VSA when the source voltage VDD is reduced due to a fluctuation of the voltage. In such case where the source voltage VSA is generated from the source voltage VDD by boosting up, an efficiency of generating the voltage becomes deteriorated largely. In the meantime, if the source voltage VSA is generated without boosting up, an operation speed of the sense amplifier becomes deteriorated. It is therefore desired to achieve a technique which can supply the source voltage efficiently without deteriorating the operation speed of the sense amplifier and without being affected by the operation limit voltage.